1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a method and apparatus for testing a semiconductor memory device having a plurality of memory banks, by which the physical address of a defective memory cell can be found easily.
2. Description of the Related Art
Recently, a combined semiconductor memory device, i.e., a memory merged with a logic circuit (MML), has developed rapidly.
In highly integrated memories, redundant line analysis is performed, by which a high yield can be expected.
Here, since data input/output pins in a memory included in the MML are formed in plural formats, for example, .times.64 , .times.128, .times.256, .times.512, .times.1024, and so on, the memory operates fast. At this time, due to the limit in the number of input/output pins of a memory testing apparatus, the multiple input/output memory cannot be tested. Also, due to the limit in generation of patterns by an algorithmic pattern generator, a logic circuit testing apparatus cannot test a highly integrated memory.
Thus, currently, the memory is directly accessed in a mode register setting method so that a plurality of data input/output lines are allocated to representative data output pins to test the memory in .times.4, .times.8, .times.16, and so on.
For example, a 16-MB DRAM having 64 data input/output lines multiplexes the data input/output lines at a ratio of 8 to 1 in the mode register setting method during a direct access test mode, so that data is input from and output to 8 data pins.
A conventional DRAM testing apparatus comprises an error catching portion, a pattern generator, a comparator, and a data detector. The memory cells are tested by writing data to the memory cells according to an address pattern and data pattern generated by the pattern generator, and reading the data.
Thus, in a semiconductor memory device having a plurality of memory banks such as MML or synchronous DRAM, the separate memory banks are not differentiated. Thus, in the case of testing the memory cells using the DRAM testing apparatus, it is not possible to find which memory bank includes a defective memory cell. Also, since data is output to only a representative data pin among various data pins, by the MRS mode setting method, it is not possible to know through which data input/output line the data is output.
FIG. 1 shows the memory structure of a semiconductor memory device having a plurality of memory banks.
Referring to FIG. 1, the semiconductor memory device includes memory banks Bank1 and Bank2 each having 8 memory blocks Blocks 0 through 7 and Blocks 8 through 15.
The memory blocks Blocks 0 through 15 each include two memory cell arrays. Each of the memory cell arrays includes memory cells allocated to 9-bit row addresses X0 through X255 or X256 or X511, 8-bit column addresses Y0 through Y255, and physical addresses composed of the row and column addresses, two row redundancy lines RR and four column redundancy lines for repairing a defective memory cell if any.
FIG. 2 is a schematic diagram illustrating how the semiconductor memory device shown in FIG. 1 is tested.
Referring to FIG. 2, a conventional memory testing apparatus 12 includes an error catching portion 22, e.g., an error catch RAM. The error catching portion 22 stores test results for the memory blocks of a semiconductor memory device 11.
In more detail, the error catching portion 22 is divided into four addresses, and each address stores either the physical address of a defective memory cell of a memory portion 21 or the number of a data pin through which the data is output from the memory cell for the physical address, i.e., one of data pins DQ0 through DQ3.
For example, the physical addresses of defective memory cells of the memory blocks Block0, Block2, Block8 and Block10 in which the eighth bit of the row address bit 8, i.e., RA8, is logic low ("0") and the data is output through a data in DQ0 or DQ3, and the numbers of the data pins, are stored in the first address of the error catching portion 22. Also, the physical addresses of defective memory cells of the memory blocks Block 5, Block7, Block13 and Block15 in which the eighth bit of the row address, i.e., RA8, is logic high ("1") and the data is output through a data pin DQ1 or DQ2, and the numbers of the data pins, are stored in the fourth address of the error catching portion 22.
The physical address of any failing memory cell is replaced by a row redundant line or column redundant line, according to the information stored in the error catching portion 22.
However, since the information for four memory blocks is repeatedly stored, it is not possible to know which one of the memory blocks contains the defective cell.
For example, if data failure information appears in the first address of the error catching portion 22, it is not possible to know which memory block among the memory blocks 0, 2, 8 and 10 includes the defective memory cell. Also, when the memory cells of different physical addresses are tested in the memory blocks 0, 2, 8 and 10, since the different physical addresses overlap one another in the error catching portion 22, the physical address at which data failure actually occurs cannot be found. Thus, it is difficult to analyze bit failure.